This article mainly leads to：RVV benchmark Milk-V Pioneer RVV benchmark Milk-V Pioneer (SG2042, C920)
RISC-V Vector benchmark
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code.
Benchmark results can be found at: RVV benchmark
Benchmarks (./bench/)
Contains a bunch of benchmark of different implementations of certain algorithms.
RVV code is currently only written in assembly, and uses ./thiredparty/rvv-rollback.S to support RVV 0.7.1 and RVV 1.0, because there currently isn’t any RVV 1.0 hardware easily available.
Instruction cycle count (./instructions/)
Measures the cycle count of RVV instructions by unrolling and looping over the given instruction repeatedly.
This currently only supports RVV 0.7.1 and was written for the C906 and C920 processors.
Getting started
Start out by configuring ./config.mk such that make works and optionally ./run.sh, which allows you to compile and run using make run.
If you have a rvv 0.7.1 supporting board (which is as of now almost certain), make sure to use a rvv 0.7.1 compatible toolchain. I’ve used this one for development.
Running benchmarks (./bench/)
To run the benchmarks, first look through (./bench/config.h) and adjust it to your processor (e.g. set HAS_E64). If it takes to long to execute, try lowering MAX_MEM, which is used to scale the benchmark, and play around with the other constants until it executes in a reasonable amount of time and gives a relatively smooth graph.
Now you can just run the benchmarks using make run in the (./bench/) directory, or make to just build the executables.
Measuring cycle count (./instructions/)
This is currently only supported for RVV 0.7.1.
To run the cycle count measurement, first configure instructions/thead-0.7.1/config.h to your processor.
Now you can just run the measurement using make run in the (./instructions/thead-0.7.1/) directory, or make to just build the executables.
Contributing
Here are some suggestions of things that still need to be done.
- contribute a measurement of a new CPU to: GitHub - camel-cdr/rvv-bench-results: A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
You can just create an issue with a single json file, which contains all concatinated ./bench/ results. (after proper setup,make run > out.jsonshould do the trick). \ - implement non memory bound benchmarks
- implement more benchmarks
- cycle count for RVV 1.0
- cycle count for load/stores
- cycle count for vsetvl
License
This repository is licensed under the MIT LICENSE.